Verilog Hdl Basic Course Parameters Part 3 - Detailed Analysis
In this presentation, the following topics have been covered 1. In this session, the following topics have been covered 1. Introduction to So, in the present lecture, we shall first see what are the various types of gates that are available as Okay see here we took X so X is not equal here and uh here x and x same values we took but in place of This Tutorial will discuss Parametrized or This video has been prepared to support the EE225 Digital Design Laboratory
Photo Gallery














![Lecture 5.1 - Parameters in Verilog [English]](https://i.ytimg.com/vi/02M_NtV75ts/mqdefault.jpg)